1. Field of the Invention
The present invention relates to semiconductor fabrication techniques, more particularly, to a semiconductor device having a cylindrical type capacitor and a method for fabricating the same.
2. Background of the Invention
Recent trends towards reducing the minimum critical dimension and achieving higher degrees of integration in semiconductor devices have resulted in reducing the unit cell areas and therefore resulted in reducing the available area for a cell capacitor. No matter how small the area for a cell capacitor can be, a capacitance required for a unit cell still needs to be ensured in the capacitor within a cell. Therefore, a number of methods have been proposed to form a capacitor having a high capacitance within the limited available area. Among these methods are technique for developing a high-k dielectric to secure a high capacitance, and methods for stably forming capacitors that do not cause defects in a semiconductor device when these capacitors have large aspect ratios. However, the formation stable capacitor structures in semiconductor devices with the demands of sub-50 nm design rules have been difficult.
In the art, a cylindrical type capacitor has been introduced to ensure a large capacitor area per unit cell, but an increase in the planar area according to a given design rule is limited. Therefore, the only way to ensure a desired capacitance has been to increase the height of a capacitor.
In case of increasing the height of such a cylindrical type capacitor, a step (or level) difference between the cell region and the peripheral region after the formation of an upper electrode gets larger which requires the deposition of a relatively thick interlayer dielectric. However, during a subsequent planarization process such as CMP (chemical mechanical polishing), the cylindrical capacitor is subjected to undesirable stresses due to the large thicknesses of the interlayer dielectric which makes the cylindrical capacitor prone to cracking. Also, a cylindrical capacitor structure where only the cell region undergoes the dip-out process has been adopted to reduce a CD (critical dimension) bias during the formation of a metal plug. Considering that a step difference between the cell region and the peripheral region gets smaller after the dip-out process on the cell region, it is possible to reduce the overlap between a cell mat and an upper capacitor electrode, thereby achieving a net die increase.
According to the conventional technique described above, to dip out only the cell region, a guard ring is needed to be formed at the boundary of the peripheral region which adjoins to the cell region so as to protect a storage node oxide in the peripheral region when removing the storage node oxide. That is, the storage node oxide in the peripheral region should not be removed during the removal of the storage node oxide. However, if the structure is weak to any extent at all (e.g., the guard ring formed at the boundary of the peripheral region adjoined to the cell region has a defect), cracks can be formed therein or lifting may occur at the interface between the guard ring and the support film. As a result thereof, the storage node oxide in the peripheral region is not protected and an oxide etchant during the wet dip-out process permeates into the weak part, thereby bringing damage to the storage node oxide film. Such a defect is called a bunker defect.
FIG. 1a and FIG. 1b illustrate the occurrence of a defect during the formation of a cylindrical type capacitor according to the art. As shown in FIG. 1a, when a defect occurs in the guard ring formed at the boundary of the peripheral region adjoined to the cell region, the etchant can permeate during the wet dip-out process which can damage the storage node oxide as shown in the portion indicated within the dotted line.
Therefore, when the storage node oxide is damaged as described above, a metal contact which contacts both the top of the upper electrode and the bit lines during the subsequent multi level metal (MLM) formation process experiences a short, which in turn causes a defective operation of the semiconductor device and further reduces the yield of the semiconductor devices.